Scan based test technology provides a way to structurally test digital integrated chips, as described by Eichelberg in U.S. Pat. No. 3,784,907, and Zasio et al. in U.S. Pat. No. 4,495,629. These and other patents teach that when all internal state variables are scanned, the remaining logic of an integrated circuit can be fully tested as if it were purely combinatorial. This approach provides significantly more predictable results compared to the uncertain result of obtained using sequential testing. Unfortunately, scan testing is time consuming. For each test pattern, the entire internal state of the integrated chip must be scanned in, one bit per clock cycle, before a system clock can be issued, and then the resulting internal state must be scanned out, again, one bit at a time. Earlier, the number of clock cycles necessary to perform scan-based testing was not considered a problem since the scan-in and scan-out cycles of successive test patterns were overlapped, the number of test patterns was small, and the scan strings (also termed “scan chains”) were not very long. On the other hand, present day designs may contain as many as 250,000 to 2.5 million internal state variables that require scan-in for initialization and scan-out for observing their values after each test pattern. Thus, total number of test clock cycles and the number of bits of scan-based test data for large IC's have major impact on memory requirements for testers and total test time, which is crucial in determining IC test costs.
Several techniques were developed to help combat the increased test data volume and tester clock cycle requirements. For example, Built-in self test, or BIST as described in Agrawal, V. et al., “A Tutorial on Built-In Self Test, Part 1: Principles”, IEEE Design & Test of Computers, March 1993, and Agrawal, V. et al., “A Tutorial on Built-In Self Test, Part 2: Applications”, IEEE Design & Test of Computers, June 1993 have been suggested to help reduce the amount of time necessary to load and unload the scan chains. BIST targets loading the BIST engine with a starting state that creates the initial test vector, and then clocking the system as many times as necessary to get the desired coverage so that the final result may be scanned out to determine its check-sum. During its operation, the BIST engine creates a new pseudo-random test vector for each new test cycle and the check-sum is used as a condensed version of the result that has been reduced to a few bits. By reducing the need for external test data, BIST significantly improves the test data volume, through it does not produce good tests for arbitrary logic. As a result, it is primarily only used for memories and similar regular structures, where acceptable test coverage may be achievable. Furthermore, BIST leads to increased test time (i.e., total number of test-clock cycles) since it still requires each pseudo-random test pattern to be scanned-in to, and the results to be scanned-out of, the scan chains and, typically, more patterns are required to achieve coverage attainable using deterministic test patterns, such as using an automatic test pattern generator (ATPG) program.
This has still left unsolved the problem of applying regular scan-based test patterns in a faster way.
The most common technique to reduce test time is to break up the single long scan string into multiple shorter scan strings. While this technique reduces overall test time, it increases the number of pins required for the scan-in of the internal states since each individual scan chain requires a separate pair of scan-in and scan-out pins. One approach to reduce the total number of scan-in and scan-out pins is to eliminate all external (to the IC device under test) scan-out pins and use an internal signature register to capture the scan-out values. For example, see the approach described by Barnhart et al in “OPMISR: The Foundation for Compressed ATPG Vectors”, ITC International Test Conference, paper 27.4, Baltimore Md., Oct. 30-Nov. 1, 2001. A different approach, which aims at reducing the number of external scan-in pins is described by Rajski et al. in U.S. Pat. No. 5,991,909. In this approach, data compression techniques are used to codify the input scan in values in such a fashion that an on-chip data decompressor can be utilized to expand data received at “n”-many scan-in terminals so it can be applied as input to “m”-many scan-in chains. Thus, by choosing “m” greater than “n”, it is possible to implement “m”-many internal scan chains which are fed serial data from only “n”-many scan-in pins. Increasing the effective number of internal scan chains which are scanned in parallel results in shorter length chains and reduces the total test time since fewer shift cycles are needed to scan the chains completely. Rajski uses an Exclusive-OR gating structure to combine (i.e., compress) the scan-out values from the m-many internal scan chains into n-many scan-out pins. By using a “decompressor” at the scan inputs and a “compressor” at the scan outputs, Rajski translates the m-many internal scan chains into n-many externally visible scan chains and effectively loads/unloads the scan chains by dealing with the shorter length of the m-many internal chains while using the smaller number of n-many scan-in/scan-out signal pin pairs. This technique reduces the test time and the number of test pins by creating m-many internal scan chains, which are shorter (by a factor of m/n) than the n-many externally visible scan chains. However, this technique still requires that each of the internal scan chains must still be completely scanned in order to load each test pattern and simultaneously unload test results from the previous test pattern.
The present invention reduces this fundamental scan shifting time further by utilizing the results that already exist in the internal scan strings from the prior pattern in order to form the next test pattern. The present invention can be implemented either on its own or together with other techniques that may be used to increase the number of internal scan chains. This is possible based on the observation, which is known to those who are knowledgeable in the state of art, that most of the test patterns require a small percentage (typically less than 10%) of the internal state variables to be set to pre-determined values, and furthermore, that the expected results can be captured into even fewer number internal state variables. This is due to the fact that even in large IC's that have very many internal state variables that are scannable, the first few test patterns are often successful in detecting a high percentage (up to 85%) of the faults. The remaining large percentage (greater than 90%) of test patterns are targeted to detect a small percentage (e.g. 15%) of all of the faults in the target IC that remain to be detected. Many of the state variables are not utilized in these patterns since the faults that require these state variables to be set to specific values have already been detected.
In each test vector, state variables that must be set to specific values are called “care inputs”. Accordingly, the present invention shifts new values into the scan string (or strings) until all of the “care inputs” of the present test vector have been simultaneously set to their required values, either by providing the required values using serial scan-in pins, or by utilizing the existing values in the scan strings that are left over results from the application of a previous test. Utilizing existing values in the scan strings enables scanning less than the entire length of the scan chain and therefore reduces the number of scan cycles and the total test time. In each test result vector, state variables that have captured values that are material in detecting some of the remaining faults in the target IC as called “care outputs”. Following the serial shift operations to establish the next test pattern and the subsequent capture of the test results, captured test results are only shift towards the outputs of the scan chains for as many bit positions as needed in order for the “care outputs” to be captured in a check-sum using multiple taps from each scan string. Accordingly, the present invention shifts test results out of the scan chains until all of the “care outputs” for the given results vector have been captured via check-sum circuitry into a signature register. The number of serial shift cycles necessary for each test pattern is variable and is dependent on the number of shift cycles necessary to achieve the desired values of the “care inputs” and the number of shift cycles necessary to capture the “care outputs” in a checksum or signature register. A probabilistic analysis of this approach, presented below, shows the target IC can be tested using less than ⅕ of the shift clock cycles being required in previous scan techniques. Test time is significantly reduced with minimal overhead to any of the existing techniques.
The primary objective of the present invention is to reduce the volume of test data, as defined by the number of scan-in values and scan-out values as well as reducing the application time, as expressed in number of test clock cycles necessary to exchange the test data between the target IC and an external tester. Present invention achieves this objective in two ways. First, test results for each test vector are captured on the “care outputs” of each test vector and the captured values are observed by performing a scan-out of the internal scan chains until all “care outputs” have been observed. Since a scan-out of the internal scan chains is avoided after all of the “care outputs” have been observed (but before all of the bits of the internal scan chains have been scanned out) the total number of scan-out clock cycles and the scan-out test data volume are reduced. Furthermore, the observation of the “care outputs” is accelerated by selecting “tap-out” points (i.e., bit positions along the scan-chains) and feeding data from the “tap-out” points into a Multi-Input Signature Register (MISR). This technique reduces the maximum number of scan-out cycles needed to observe all of the “care outputs” to the maximum bit separation between any two consecutive “tap-out” points (or between the first “tap-out” point and the serial “scan-in” input terminal or the last “tap-out” point and the “scan-out” terminal). This technique allows the designer to select the number of “tap-out” points in order to achieve the desired reduction in the number of scan-out cycles and the corresponding reduction in the overall scan-out data volume.
Secondly, the “care inputs” for each test vector are set using either the values already present in the internal scan chains, or a combinatorial combination of the values present in the internal scan chains and the serial data at the scan-in terminal to each internal scan chain. A value that is already present in the scan chain can be seen as representing a value applied at the serial scan-in terminal at “k” cycles previous to the present, where “k” is the number of bit positions between the bit position that contains said value and the serial scan-in terminal. By using the stored value in setting a “care input” to the value required by the test vector, the initial “k” shift cycles are bypassed, accelerating the overall scan-in process. Furthermore, since scan-in values are not needed for the initial “k” cycles, the total scan-in data volume is also reduced. Data from a common scan-in terminal or multiple data from several independent scan-in terminals are fed forward to merge with the data already in the scan chain. This technique bypasses sections of the scan-chain so that bit positions further away from the starting point of the scan chain receive values from the starting point of the scan chain more quickly. By accelerating the movement of serial data to the downstream positions of the scan chain, the number of scan-in cycles necessary to set a “care input” value from the serial input terminal is reduced.
In addition to the acceleration of the observation of the “care outputs” and the setting of the “care inputs”, the observation of the “care outputs” and the setting of the “care inputs” do not require an identical number of scan cycles. This is a feature not found in state-of-art scan techniques for applying pre-determined and/or deterministic test vectors. Thus, the number of “tap out” points can be different from the number of “feed forward” positions, as long as for each test vector the number of scan cycles to set the “care inputs” is at least as large as the number of scan cycles needed to observe all of the “care outputs” since these two operations are performed in overlapped fashion. The “care outputs” from the last test vector are being observed while the “care inputs” for the next test vector are being set. Hence, the total number of scan cycles at each vector may be different. All existing scan-based test methods up to now require the same number of scan cycles for all scan-out and scan-in operations. The cycle count is equal to the number of bits along the scan chain so that it is constant for all test vectors. This approach is different from dynamically reconfiguring the scan chains so that an increased number of shorter scan chains may be formed and operated in parallel. In contrast to the present invention, dynamic reconfiguration achieves only a change in the total number of scan cycles without achieving a reduction in the total scan-in/scan-out data volume. Indeed, the present invention can be applied on top of any existing serial scan structure and still achieve reductions of test data volume and scan cycle count.
A probability analysis of the technique presented here is also provided. The analysis assumes a fixed percentage of “care inputs” randomly chosen and set to randomly chosen values. It calculates the expected number of serial scan operations for a given vector necessary to simultaneously set the “care inputs” to their selected values. Indeed, the probability calculations show serial scan-in cycles which are much shorter than the total length of the internal scan chain. These results strongly suggest that pseudorandom, rather than deterministic values may be fed into the serial scan-in terminal (or multiple scan-in terminals). Pseudorandom values can be created very easily using an on-chip generator, such as a Linear Feedback Shift Register. Thus, the present invention teaches a technique for use in Built-In Self Test (BIST) applications, as well as for test applications using pre-determined test vectors.
In summary, the present invention provides for the capture of test results from the “care outputs” of each test vector while all of the “care inputs” of the next test vector are set to their required values with a reduced number of serial shift operations. This results in a reduced volume of test data for testing the target device. Additionally, the present invention provides for feed-forward paths within the scan chains to further reduce the number of serial shift operations necessary to set all of the “care inputs” to the values required for each test vector.
In much of the specification below, descriptions are given with respect to a serial scan chain. Where a target IC implements multiple (parallel) internal scan chains, the descriptions given here should be taken to apply to each serial scan chain. Furthermore, features are described that allow starting and stopping the serial shift operations along the individual scan chains separately from the other chains so that the chains can be operated independently. This allows serial shifting of each scan chain until all of its “care outputs” have been observed and all of its “care inputs” have been set to the required values without requiring that the total number of shift cycles be the same for all scan chains.